of_sec_lc_ctrl
Lifecycle controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Lifecycle state machine (raw, test, production, RMA, scrap) with token-based transitions and broadcast enables to debug and keys.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| lc_en | out | parallel | 16 |
Standards
No external standard applies.
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in lifecycle
| ID | Block | Maturity |
|---|---|---|
| of_sec_otp_ctrl | OTP controller | planned |
| of_sec_rollback_counter | Anti-rollback counter | planned |
| of_sec_bbram_rtc | Battery-backed key store with tamper inputs | planned |