of_sec_bbram_rtc
Battery-backed key store with tamper inputs
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Battery-domain SRAM for keys with a secure RTC and tamper pins that erase contents on detection.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| tamper_in | in | parallel | 4 |
Standards
- NIST FIPS 140-3
More in lifecycle
| ID | Block | Maturity |
|---|---|---|
| of_sec_otp_ctrl | OTP controller | planned |
| of_sec_lc_ctrl | Lifecycle controller | planned |
| of_sec_rollback_counter | Anti-rollback counter | planned |