of_sec_hash_drbg
Hash_DRBG and HMAC_DRBG
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
SHA-2 based Hash_DRBG and HMAC_DRBG for systems that standardise on hash primitives.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| seed_in | in | valid-qualified bus | 384 | |
| rnd_out | out | valid-qualified bus | 256 |
Standards
- NIST SP 800-90A Rev. 1
More in rng
| ID | Block | Maturity |
|---|---|---|
| of_sec_trng_ro | Ring-oscillator entropy source | planned |
| of_sec_trng_noise | Thermal-noise entropy source | planned |
| of_sec_entropy_health | Entropy health tests and conditioner | simulated |
| of_sec_ctr_drbg | CTR_DRBG | simulated |
| of_sec_entropy_dist | Entropy distribution network | planned |