of_sec_ctr_drbg
CTR_DRBG
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
AES-256 CTR_DRBG with instantiate, reseed, generate and uninstantiate commands and multiple application interfaces.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| seed_in | in | valid-qualified bus | 384 | |
| rnd_out | out | valid-qualified bus | 128 |
Standards
- NIST SP 800-90A Rev. 1
- NIST SP 800-90C
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in rng
| ID | Block | Maturity |
|---|---|---|
| of_sec_trng_ro | Ring-oscillator entropy source | planned |
| of_sec_trng_noise | Thermal-noise entropy source | planned |
| of_sec_entropy_health | Entropy health tests and conditioner | simulated |
| of_sec_hash_drbg | Hash_DRBG and HMAC_DRBG | planned |
| of_sec_entropy_dist | Entropy distribution network | planned |