IP PortfolioSecurityroot_of_trust
of_sec_enclave
Secure enclave subsystem
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Isolated processor with private SRAM, crypto engines and a filtered mailbox to the host for key and credential operations.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
More in root_of_trust
| ID | Block | Maturity |
|---|---|---|
| of_sec_boot_rom | Secure boot ROM controller | simulated |
| of_sec_rot | Discrete-class root of trust subsystem | planned |
| of_sec_rot_soc | Integrated SoC root of trust | planned |
| of_sec_hsm_auto | Automotive hardware security module | planned |
| of_sec_tpm | TPM 2.0 core | planned |
| of_sec_selftest | Cryptographic self-test sequencer | planned |
| of_sec_mailbox | Access-controlled security mailbox | planned |