IP PortfolioSecurityroot_of_trust
of_sec_boot_rom
Secure boot ROM controller
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Boot ROM wrapper that scrambles ROM contents and computes a digest at reset before releasing the core, plus a signature verification flow in ROM code.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
- NIST SP 800-193
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in root_of_trust
| ID | Block | Maturity |
|---|---|---|
| of_sec_rot | Discrete-class root of trust subsystem | planned |
| of_sec_rot_soc | Integrated SoC root of trust | planned |
| of_sec_enclave | Secure enclave subsystem | planned |
| of_sec_hsm_auto | Automotive hardware security module | planned |
| of_sec_tpm | TPM 2.0 core | planned |
| of_sec_selftest | Cryptographic self-test sequencer | planned |
| of_sec_mailbox | Access-controlled security mailbox | planned |