IP PortfolioQuantum controlphotonic
of_q_feedforward
Feed-forward switch controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Low-latency logic that maps detection patterns to electro-optic switch and phase settings within the photon delay budget.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| click_in | in | parallel | 32 | |
| sw_out | out | parallel | 32 |
Standards
No external standard applies.
More in photonic
| ID | Block | Maturity |
|---|---|---|
| of_q_snspd_readout | SNSPD readout front end | planned |
| of_q_spad_ctrl | SPAD gating and quench controller | planned |
| of_q_time_tagger | Multi-channel time tagger | planned |
| of_q_coincidence | Coincidence counter | simulated |
| of_q_tcspc_hist | TCSPC histogrammer | planned |
| of_q_source_mux | Heralded source multiplexing controller | planned |
| of_q_pnr_analyser | Photon-number pulse analyser | planned |
| of_q_qkd_postproc | QKD post-processing engine | planned |
| of_q_qrng_frontend | Quantum RNG readout and extractor | planned |
| of_q_mbqc_ctrl | Measurement-based computation controller | planned |