IP PortfolioProcessorsriscv_multithread
of_cpu_smt2_ooo_ext
Two-way SMT extension
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Simultaneous multithreading option for the out-of-order core that duplicates architectural state and partitions or shares queues between two harts.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- RISC-V RV64GC
More in riscv_multithread
| ID | Block | Maturity |
|---|---|---|
| of_cpu_mt_barrel | Fine-grained multithreaded core | planned |