IP PortfolioProcessorsriscv_multithread
of_cpu_mt_barrel
Fine-grained multithreaded core
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Barrel-processor RV32 core interleaving four to eight hardware threads cycle by cycle, hiding memory latency for packet and I/O processing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 |
Standards
- RISC-V RV32IMA
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in riscv_multithread
| ID | Block | Maturity |
|---|---|---|
| of_cpu_smt2_ooo_ext | Two-way SMT extension | planned |