IP PortfolioProcessorsinterrupt
of_cpu_mailbox
Inter-processor mailbox and semaphores
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Doorbell mailboxes, message FIFOs and hardware semaphores for communication between harts and heterogeneous cores.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
More in interrupt
| ID | Block | Maturity |
|---|---|---|
| of_cpu_plic | Platform-level interrupt controller | simulated |
| of_cpu_aclint | Core-local interruptor (ACLINT) | simulated |
| of_cpu_clic | Core-local interrupt controller (CLIC) | simulated |
| of_cpu_aia | Advanced interrupt architecture (APLIC and IMSIC) | planned |