IP PortfolioProcessorsinterrupt
of_cpu_aia
Advanced interrupt architecture (APLIC and IMSIC)
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
APLIC for wired interrupts and IMSIC message-signalled interrupt files with guest interrupt files for virtualised systems.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| src | in | parallel | 256 |
Standards
- RISC-V AIA 1.0
More in interrupt
| ID | Block | Maturity |
|---|---|---|
| of_cpu_plic | Platform-level interrupt controller | simulated |
| of_cpu_aclint | Core-local interruptor (ACLINT) | simulated |
| of_cpu_clic | Core-local interrupt controller (CLIC) | simulated |
| of_cpu_mailbox | Inter-processor mailbox and semaphores | planned |