IP PortfolioInterface PHYslvds_io
of_sublvds_rx
Sub-LVDS receiver
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Low common-mode, reduced-swing differential receiver array for CMOS image sensor outputs with deserializer and word alignment.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| rxd | in | differential pair | 8 | |
| par_rx | out | parallel | 64 | |
| clk_in | in | differential pair | 1 |
Standards
No external standard applies.
More in lvds_io
| ID | Block | Maturity |
|---|---|---|
| of_lvds_serdes | Source-synchronous LVDS SerDes | planned |
| of_slvs400_io | SLVS-400 I/O | planned |
| of_mlvds_io | M-LVDS multipoint transceiver | planned |
| of_fpdlink_tx_phy | 7:1 LVDS display serializer PHY | planned |
| of_sgmii_lvds_phy | SGMII over LVDS PHY | planned |