IP PortfolioInterface PHYslvds_io
of_fpdlink_tx_phy
7:1 LVDS display serializer PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
Display serializer with 7x PLL and 4 or 5 LVDS data pairs plus clock pair for OpenLDI/FPD-Link panels in single and dual link.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| lvds | out | differential pair | 5 | |
| lvds_clk | out | differential pair | 1 | |
| par_tx | in | parallel | 35 | |
| pclk | in | clock | 1 |
Standards
- TIA/EIA-644-A
- OpenLDI 0.95
More in lvds_io
| ID | Block | Maturity |
|---|---|---|
| of_lvds_serdes | Source-synchronous LVDS SerDes | planned |
| of_slvs400_io | SLVS-400 I/O | planned |
| of_sublvds_rx | Sub-LVDS receiver | planned |
| of_mlvds_io | M-LVDS multipoint transceiver | planned |
| of_sgmii_lvds_phy | SGMII over LVDS PHY | planned |