IP PortfolioInterface PHYsserdes
of_serdes_224g
224 Gb/s PAM4 SerDes
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
224G PAM4 SerDes for 200G-per-lane Ethernet electrical interfaces with high-resolution ADC receiver, DSP equalisation and MLSE option.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 4 | |
| rx | in | differential pair | 4 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 2048 | |
| pma_rx | out | parallel | 2048 |
Standards
- IEEE P802.3dj
Notes
Track IEEE 802.3dj and OIF CEI-224G final text before specification freeze.
More in serdes
| ID | Block | Maturity |
|---|---|---|
| of_serdes_12g | Multi-protocol SerDes up to 12.5 Gb/s | planned |
| of_serdes_32g | Multi-protocol SerDes up to 32 Gb/s NRZ | planned |
| of_serdes_56g_pam4 | 56 Gb/s PAM4 SerDes | planned |
| of_serdes_112g_lr | 112 Gb/s PAM4 long-reach SerDes | planned |
| of_serdes_112g_xsr | 112 Gb/s XSR/VSR SerDes | planned |