IP PortfolioInterface PHYsserdes
of_serdes_112g_lr
112 Gb/s PAM4 long-reach SerDes
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
112G PAM4 SerDes with ADC-based DSP receiver for long-reach backplane and copper cable channels, also covering 106G Ethernet and PCIe 6.0 rates.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 4 | |
| rx | in | differential pair | 4 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 1024 | |
| pma_rx | out | parallel | 1024 |
Standards
- IEEE 802.3ck-2022
- OIF CEI-112G-LR
More in serdes
| ID | Block | Maturity |
|---|---|---|
| of_serdes_12g | Multi-protocol SerDes up to 12.5 Gb/s | planned |
| of_serdes_32g | Multi-protocol SerDes up to 32 Gb/s NRZ | planned |
| of_serdes_56g_pam4 | 56 Gb/s PAM4 SerDes | planned |
| of_serdes_112g_xsr | 112 Gb/s XSR/VSR SerDes | planned |
| of_serdes_224g | 224 Gb/s PAM4 SerDes | planned |