IP PortfolioInterface PHYsdisplay_phy
of_hdmi21_tx_phy
HDMI 2.1 transmitter PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
HDMI 2.1 transmitter PHY supporting TMDS and FRL at 3, 6, 8, 10 and 12 Gb/s over 4 lanes with FFE levels per the FRL link training.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| lane | out | differential pair | 4 | |
| par_tx | in | parallel | 160 | |
| refclk | in | clock | 1 |
Standards
- HDMI 2.1b
More in display_phy
| ID | Block | Maturity |
|---|---|---|
| of_hdmi20_tx_phy | HDMI 2.0 TMDS transmitter PHY | planned |
| of_hdmi21_rx_phy | HDMI 2.1 receiver PHY | planned |
| of_dp14_tx_phy | DisplayPort 1.4 / eDP transmitter PHY | planned |
| of_dp21_tx_phy | DisplayPort 2.1 transmitter PHY | planned |
| of_dp_rx_phy | DisplayPort receiver PHY | planned |
| of_vbyone_phy | V-by-One HS transmitter PHY | planned |