IP PortfolioInterface PHYsdisplay_phy
of_dp_rx_phy
DisplayPort receiver PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
DisplayPort sink PHY with CDR, CTLE/DFE equalisation and AUX transceiver for 8b/10b and UHBR rates.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| lane | in | differential pair | 4 | |
| aux | inout | differential pair | 1 | |
| par_rx | out | parallel | 320 | |
| refclk | in | clock | 1 |
Standards
- VESA DisplayPort 2.1
More in display_phy
| ID | Block | Maturity |
|---|---|---|
| of_hdmi20_tx_phy | HDMI 2.0 TMDS transmitter PHY | planned |
| of_hdmi21_tx_phy | HDMI 2.1 transmitter PHY | planned |
| of_hdmi21_rx_phy | HDMI 2.1 receiver PHY | planned |
| of_dp14_tx_phy | DisplayPort 1.4 / eDP transmitter PHY | planned |
| of_dp21_tx_phy | DisplayPort 2.1 transmitter PHY | planned |
| of_vbyone_phy | V-by-One HS transmitter PHY | planned |