IP PortfolioInterface PHYsdie_to_die_phy
of_d2d_xsr_serdes
112G XSR die-to-die SerDes
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 3
Serial die-to-die PHY for chiplets on organic substrate using extra-short-reach 112G PAM4 or NRZ lanes with minimal equalisation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 16 | |
| rx | in | differential pair | 16 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 1024 | |
| pma_rx | out | parallel | 1024 |
Standards
- OIF CEI-112G-XSR
More in die_to_die_phy
| ID | Block | Maturity |
|---|---|---|
| of_ucie_phy_std | UCIe standard-package PHY | planned |
| of_ucie_phy_adv | UCIe advanced-package PHY | planned |
| of_bow_phy | BoW die-to-die PHY | planned |
| of_aib_phy | AIB PHY | planned |
| of_openhbi_phy | OpenHBI PHY | planned |