IP PortfolioInterface PHYsdie_to_die_phy
of_bow_phy
BoW die-to-die PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Bunch of Wires PHY slices with 16 data wires, forwarded clock and simple unterminated drivers for standard and advanced packages.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | parallel | 18 | |
| rx | in | parallel | 18 | |
| par_tx | in | parallel | 256 | |
| par_rx | out | parallel | 256 |
Standards
- OCP BoW 2.0
More in die_to_die_phy
| ID | Block | Maturity |
|---|---|---|
| of_ucie_phy_std | UCIe standard-package PHY | planned |
| of_ucie_phy_adv | UCIe advanced-package PHY | planned |
| of_aib_phy | AIB PHY | planned |
| of_openhbi_phy | OpenHBI PHY | planned |
| of_d2d_xsr_serdes | 112G XSR die-to-die SerDes | planned |