IP PortfolioInterface controllersuart
of_usart
USART with RS-485 and IrDA SIR
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Synchronous and asynchronous serial controller with RS-485 driver-enable timing, IrDA SIR 3/16 pulse encoding, LIN break generation, hardware flow control and DMA request lines.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| txd | out | serial | 1 | |
| rxd | in | serial | 1 | |
| sclk | out | clock | 1 | |
| de | out | serial | 1 |
Standards
- TIA/EIA-485-A
- IrDA Serial Infrared Physical Layer 1.4
More in uart
| ID | Block | Maturity |
|---|---|---|
| of_uart | UART with APB interface | fpga-routed |
| of_uart_16550 | 16550-compatible UART | simulated |