IP PortfolioInterface controllersuart
of_uart_16550
16550-compatible UART
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
UART register-compatible with the industry 16550A, including 16-byte FIFOs, modem control and status lines (RTS/CTS/DTR/DSR/DCD/RI) and scratch register, so stock OS drivers work unmodified.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| txd | out | serial | 1 | |
| rxd | in | serial | 1 | |
| modem_out | out | parallel | 2 | |
| modem_in | in | parallel | 4 |
Standards
No external standard applies.
Basis projects
Permissive open projects the implementation may build on.
- LiteX (BSD-2-Clause)