IP PortfolioInterface controllersdie_to_die
of_ucie_adapter
UCIe die-to-die adapter
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
UCIe D2D adapter with flit formats, CRC, retry, parameter exchange and link management between FDI (protocol side) and RDI (PHY side), supporting PCIe, CXL and streaming protocols.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| fdi_tx | in | AXI4-Stream | 512 | |
| fdi_rx | out | AXI4-Stream | 512 | |
| rdi_tx | out | parallel | 512 | |
| rdi_rx | in | parallel | 512 |
Standards
- UCIe 2.0
More in die_to_die
| ID | Block | Maturity |
|---|---|---|
| of_ucie_axi_bridge | AXI over UCIe streaming bridge | planned |
| of_bow_link | BoW die-to-die link layer | planned |
| of_aib_adapter | AIB adapter | planned |
| of_openhbi_link | OpenHBI link layer | planned |