IP PortfolioInterface controllersdie_to_die
of_aib_adapter
AIB adapter
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Advanced Interface Bus adapter for chiplet links with channel FIFOs, DBI, word alignment markers and calibration sequencing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phy_tx | out | parallel | 320 | |
| phy_rx | in | parallel | 320 | |
| tx | in | AXI4-Stream | 256 | |
| rx | out | AXI4-Stream | 256 |
Standards
- CHIPS Alliance AIB 2.0
More in die_to_die
| ID | Block | Maturity |
|---|---|---|
| of_ucie_adapter | UCIe die-to-die adapter | planned |
| of_ucie_axi_bridge | AXI over UCIe streaming bridge | planned |
| of_bow_link | BoW die-to-die link layer | planned |
| of_openhbi_link | OpenHBI link layer | planned |