IP PortfolioInterface controllersserdes_protocol
of_srio
Serial RapidIO endpoint
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Serial RapidIO logical, transport and physical layers with NREAD/NWRITE, doorbell and messaging transactions over 1 to 4 lanes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phy_tx | out | parallel | 128 | |
| phy_rx | in | parallel | 128 | |
| tx | in | AXI4-Stream | 128 | |
| rx | out | AXI4-Stream | 128 |
Standards
- RapidIO Specification 4.1
More in serdes_protocol
| ID | Block | Maturity |
|---|---|---|
| of_aurora_link | Aurora-compatible lightweight link | planned |
| of_interlaken | Interlaken controller | planned |
| of_spi42 | SPI-4.2 interface | planned |