IP PortfolioInterface controllersserdes_protocol
of_spi42
SPI-4.2 interface
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
OIF SPI-4 Phase 2 source and sink with 16-bit LVDS DDR data path, calendar-based FIFO status and DIP-4 parity.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| tdat | out | parallel | 16 | |
| rdat | in | parallel | 16 | |
| tx | in | AXI4-Stream | 64 | |
| rx | out | AXI4-Stream | 64 |
Standards
- OIF-SPI4-02.1
Notes
Legacy packet interface kept for NPU and framer compatibility.
More in serdes_protocol
| ID | Block | Maturity |
|---|---|---|
| of_aurora_link | Aurora-compatible lightweight link | planned |
| of_interlaken | Interlaken controller | planned |
| of_srio | Serial RapidIO endpoint | planned |