IP PortfolioInterface controllersconverter_link
of_jesd204d
JESD204D link layer
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Next-generation converter link with PAM4 lane rates, RS-FEC and updated framing for wideband RF data converters.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phy_tx | out | parallel | 512 | |
| phy_rx | in | parallel | 512 | |
| samples_tx | in | AXI4-Stream | 512 | |
| samples_rx | out | AXI4-Stream | 512 | |
| sysref | in | serial | 1 |
Standards
- JEDEC JESD204D
Notes
Confirm the published revision and feature set before design start.
More in converter_link
| ID | Block | Maturity |
|---|---|---|
| of_jesd204b | JESD204B link layer | planned |
| of_jesd204c | JESD204C link layer | planned |