IP PortfolioInterface controllersconverter_link
of_jesd204c
JESD204C link layer
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
JESD204C link layers with 64b/66b and 64b/80b encodings, multiblock alignment, CRC-12 or FEC, and SYSREF-based multi-device synchronisation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phy_tx | out | parallel | 256 | |
| phy_rx | in | parallel | 256 | |
| samples_tx | in | AXI4-Stream | 256 | |
| samples_rx | out | AXI4-Stream | 256 | |
| sysref | in | serial | 1 |
Standards
- JEDEC JESD204C
More in converter_link
| ID | Block | Maturity |
|---|---|---|
| of_jesd204b | JESD204B link layer | planned |
| of_jesd204d | JESD204D link layer | planned |