IP PortfolioDatapath and DSPsorting and selection
of_sort_network
Sorting network generator
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Bitonic or Batcher odd-even merge sorting network for N keys with payload, configurable pipelining and ascending or descending order.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| keys | in | valid-qualified bus | 512 | |
| sorted | out | valid-qualified bus | 512 |
Standards
No external standard applies.
More in sorting and selection
| ID | Block | Maturity |
|---|---|---|
| of_merge_sort | Streaming merge sorter | planned |
| of_topk | Top-K selector | planned |