IP PortfolioDatapath and DSPsorting and selection
of_merge_sort
Streaming merge sorter
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Multi-way streaming merge tree that sorts long key/value sequences in passes through external memory.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| s_in | in | AXI4-Stream | 64 | |
| m_out | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in sorting and selection
| ID | Block | Maturity |
|---|---|---|
| of_sort_network | Sorting network generator | planned |
| of_topk | Top-K selector | planned |