IP PortfolioDatapath and DSPcontrol and scheduling
of_sched_dwrr
Deficit weighted round-robin scheduler
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Packet scheduler for N queues with deficit counters, per-queue quantum, strict-priority overlay and eligibility masks.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| req | in | parallel | 32 | |
| gnt | out | valid-qualified bus | 5 |
Standards
No external standard applies.
More in control and scheduling
| ID | Block | Maturity |
|---|---|---|
| of_cnt_updown | Up/down counter | simulated |
| of_cnt_gray | Gray-code counter | simulated |
| of_cnt_johnson | Johnson counter | simulated |
| of_arb_fixed | Fixed-priority arbiter | simulated |
| of_arb_rr | Round-robin arbiter | fpga-routed |
| of_arb_wrr | Weighted round-robin arbiter | simulated |
| of_arb_matrix | Matrix (least-recently-granted) arbiter | simulated |
| of_credit_cnt | Credit counter | simulated |
| of_debounce | Debouncer | simulated |
| of_edge_detect | Edge detector | simulated |