IP PortfolioDatapath and DSPcontrol and scheduling
of_edge_detect
Edge detector
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Rising, falling and any-edge pulse detector for N signals with optional 2-4 flop input synchronizer for asynchronous inputs; all outputs are derived from flops.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| sig | in | parallel | 8 | |
| pulse | out | parallel | 8 |
Standards
No external standard applies.
More in control and scheduling
| ID | Block | Maturity |
|---|---|---|
| of_cnt_updown | Up/down counter | simulated |
| of_cnt_gray | Gray-code counter | simulated |
| of_cnt_johnson | Johnson counter | simulated |
| of_arb_fixed | Fixed-priority arbiter | simulated |
| of_arb_rr | Round-robin arbiter | fpga-routed |
| of_arb_wrr | Weighted round-robin arbiter | simulated |
| of_arb_matrix | Matrix (least-recently-granted) arbiter | simulated |
| of_credit_cnt | Credit counter | simulated |
| of_debounce | Debouncer | simulated |
| of_oneshot | One-shot (monostable) pulse generator | simulated |