IP PortfolioDatapath and DSPstorage helpers
of_queue_mgr
Multi-queue shared buffer manager
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Linked-list queue manager over a shared packet buffer with per-queue head/tail pointers, free list, occupancy limits and enqueue/dequeue interfaces.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| enq | in | AXI4-Stream | 64 | |
| deq | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in storage helpers
| ID | Block | Maturity |
|---|---|---|
| of_fifo_sync | Synchronous FIFO | fpga-routed |
| of_fifo_async | Asynchronous (dual-clock) FIFO | simulated |
| of_lifo | Synchronous stack (LIFO) | simulated |
| of_regfile | Multi-port register file | simulated |
| of_cam | Content-addressable memory (flop-based) | fpga-routed |
| of_delay_line | Shift-register delay line | simulated |
| of_tcam | Ternary CAM (logic based) | planned |
| of_pingpong | Ping-pong (double) buffer | planned |
| of_line_buffer | Image line buffer | planned |
| of_fifo_packet | Packet FIFO with commit and drop | simulated |