IP PortfolioDatapath and DSPstorage helpers
of_line_buffer
Image line buffer
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Multi-line buffer delivering vertically aligned pixel columns for KxK window operators, with configurable line length and border handling.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | AXI4-Stream | 24 | |
| m_out | out | AXI4-Stream | 120 |
Standards
No external standard applies.
More in storage helpers
| ID | Block | Maturity |
|---|---|---|
| of_fifo_sync | Synchronous FIFO | fpga-routed |
| of_fifo_async | Asynchronous (dual-clock) FIFO | simulated |
| of_lifo | Synchronous stack (LIFO) | simulated |
| of_regfile | Multi-port register file | simulated |
| of_cam | Content-addressable memory (flop-based) | fpga-routed |
| of_delay_line | Shift-register delay line | simulated |
| of_tcam | Ternary CAM (logic based) | planned |
| of_pingpong | Ping-pong (double) buffer | planned |
| of_fifo_packet | Packet FIFO with commit and drop | simulated |
| of_queue_mgr | Multi-queue shared buffer manager | planned |