IP PortfolioDatapath and DSPinteger arithmetic
of_mul_seq
Sequential shift-add multiplier
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Radix-2 or radix-4 iterative multiplier producing one or two product bits per cycle for area-critical designs; signed, unsigned and mixed-sign operands with start/done handshake.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| opnd | in | valid-qualified bus | 64 | |
| prod | out | valid-qualified bus | 64 |
Standards
No external standard applies.
More in integer arithmetic
| ID | Block | Maturity |
|---|---|---|
| of_add_ripple | Ripple-carry adder | simulated |
| of_add_cla | Carry-lookahead adder | simulated |
| of_add_csel | Carry-select adder | simulated |
| of_add_kogge_stone | Kogge-Stone parallel-prefix adder | fpga-routed |
| of_add_brent_kung | Brent-Kung parallel-prefix adder | simulated |
| of_add_sklansky | Sklansky parallel-prefix adder | simulated |
| of_addsub | Adder/subtractor with flags | simulated |
| of_inc | Incrementer / decrementer | simulated |
| of_abs | Absolute value | simulated |
| of_cmp | Magnitude comparator | simulated |