IP PortfolioDatapath and DSPinteger arithmetic
of_add_ripple
Ripple-carry adder
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
WIDTH-bit ripple-carry adder built from explicit full-adder cells, {co, s} = a + b + ci. Minimum area, linear carry delay.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | parallel | 32 | |
| b | in | parallel | 32 | |
| y | out | parallel | 32 |
Standards
No external standard applies.
More in integer arithmetic
| ID | Block | Maturity |
|---|---|---|
| of_add_cla | Carry-lookahead adder | simulated |
| of_add_csel | Carry-select adder | simulated |
| of_add_kogge_stone | Kogge-Stone parallel-prefix adder | fpga-routed |
| of_add_brent_kung | Brent-Kung parallel-prefix adder | simulated |
| of_add_sklansky | Sklansky parallel-prefix adder | simulated |
| of_addsub | Adder/subtractor with flags | simulated |
| of_inc | Incrementer / decrementer | simulated |
| of_abs | Absolute value | simulated |
| of_cmp | Magnitude comparator | simulated |
| of_minmax | N-input min/max with index | simulated |