IP PortfolioDatapath and DSPnumber theory
of_mont_mul
Montgomery modular multiplier
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Word-serial or fully parallel Montgomery multiplication (CIOS and FIOS schedules) for odd moduli up to 4096 bits, with pre-computation of R^2 mod m.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| opnd | in | AXI4-Stream | 64 | |
| y | out | AXI4-Stream | 64 |
Standards
No external standard applies.
More in number theory
| ID | Block | Maturity |
|---|---|---|
| of_mod_addsub | Modular adder and subtractor | planned |
| of_barrett_red | Barrett modular reducer | planned |
| of_ntt_butterfly | Number-theoretic transform butterfly and engine | planned |