IP PortfolioDatapath and DSPnumber theory
of_barrett_red
Barrett modular reducer
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Barrett reduction of a 2n-bit product modulo an n-bit modulus with a precomputed reciprocal; constant-modulus specialization for NTT-friendly primes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| x | in | valid-qualified bus | 128 | |
| y | out | valid-qualified bus | 64 |
Standards
No external standard applies.
More in number theory
| ID | Block | Maturity |
|---|---|---|
| of_mod_addsub | Modular adder and subtractor | planned |
| of_mont_mul | Montgomery modular multiplier | planned |
| of_ntt_butterfly | Number-theoretic transform butterfly and engine | planned |