IP PortfolioDatapath and DSPdsp filters
of_fir_polyphase
Polyphase decimator and interpolator
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Polyphase FIR for integer decimation or interpolation with time-shared multipliers and multiple channels.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| s_in | in | AXI4-Stream | 32 | |
| m_out | out | AXI4-Stream | 32 |
Standards
No external standard applies.
More in dsp filters
| ID | Block | Maturity |
|---|---|---|
| of_fir | FIR filter | simulated |
| of_cic | CIC decimator and interpolator | simulated |
| of_halfband | Half-band filter | planned |
| of_iir_biquad | IIR biquad cascade | planned |
| of_farrow | Fractional resampler (Farrow) | planned |
| of_lms | Adaptive LMS / NLMS filter | planned |