IP PortfolioDatapath and DSPdsp filters
of_cic
CIC decimator and interpolator
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Cascaded integrator-comb filter with configurable order, differential delay and run-time rate change, with Hogenauer bit pruning and output gain normalization.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | AXI4-Stream | 16 | |
| m_out | out | AXI4-Stream | 32 |
Standards
No external standard applies.
More in dsp filters
| ID | Block | Maturity |
|---|---|---|
| of_fir | FIR filter | simulated |
| of_fir_polyphase | Polyphase decimator and interpolator | simulated |
| of_halfband | Half-band filter | planned |
| of_iir_biquad | IIR biquad cascade | planned |
| of_farrow | Fractional resampler (Farrow) | planned |
| of_lms | Adaptive LMS / NLMS filter | planned |