IP PortfolioDatapath and DSPencoding and line coding
of_enc_manchester
Manchester and differential Manchester codec
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 3
Manchester (IEEE and G.E. Thomas conventions) and differential Manchester encoder with oversampling decoder, clock recovery and violation detection.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | valid-qualified bus | 1 | |
| line | out | serial | 1 |
Standards
- IEEE 802.3
More in encoding and line coding
| ID | Block | Maturity |
|---|---|---|
| of_enc_8b10b | 8b/10b encoder and decoder | simulated |
| of_enc_64b66b | 64b/66b encoder, decoder and block lock | simulated |
| of_enc_128b130b | 128b/130b encoder and decoder | planned |
| of_scrambler | Scrambler and descrambler family | planned |
| of_enc_nrzi_stuff | NRZI and bit-stuffing codec | planned |
| of_enc_4b5b_mlt3 | 4B/5B and MLT-3 line coder | planned |
| of_checksum | Internet, Fletcher and Adler checksum engine | planned |