IP PortfolioDatapath and DSPencoding and line coding
of_enc_64b66b
64b/66b encoder, decoder and block lock
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
64b/66b block coding with sync-header insertion, self-synchronous x^58 scrambler, block lock state machine and gearbox to 32 or 64-bit PMA width.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | valid-qualified bus | 72 | |
| m_out | out | valid-qualified bus | 66 |
Standards
- IEEE 802.3
More in encoding and line coding
| ID | Block | Maturity |
|---|---|---|
| of_enc_8b10b | 8b/10b encoder and decoder | simulated |
| of_enc_128b130b | 128b/130b encoder and decoder | planned |
| of_scrambler | Scrambler and descrambler family | planned |
| of_enc_manchester | Manchester and differential Manchester codec | planned |
| of_enc_nrzi_stuff | NRZI and bit-stuffing codec | planned |
| of_enc_4b5b_mlt3 | 4B/5B and MLT-3 line coder | planned |
| of_checksum | Internet, Fletcher and Adler checksum engine | planned |