IP PortfolioDatapath and DSPcode conversion
of_bin2onehot
Binary to one-hot decoder
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Binary to one-hot decoder with enable; out-of-range codes decode to zero.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | parallel | 5 | |
| y | out | parallel | 32 |
Standards
No external standard applies.
More in code conversion
| ID | Block | Maturity |
|---|---|---|
| of_bin2gray | Binary to Gray converter | fpga-routed |
| of_gray2bin | Gray to binary converter | simulated |
| of_onehot2bin | One-hot to binary encoder | simulated |