IP PortfolioDatapath and DSPcode conversion
of_bin2gray
Binary to Gray converter
Maturity fpga-routedTargets FPGA + ASICDifficulty EasyPriority 1
Binary to reflected-binary Gray code, g = b ^ (b >> 1).
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| a | in | parallel | 16 | |
| y | out | parallel | 16 |
Standards
No external standard applies.
More in code conversion
| ID | Block | Maturity |
|---|---|---|
| of_gray2bin | Gray to binary converter | simulated |
| of_bin2onehot | Binary to one-hot decoder | simulated |
| of_onehot2bin | One-hot to binary encoder | simulated |