Spiking neuron core

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2

Event-driven core with leaky integrate-and-fire neurons, synaptic weight memory and optional on-chip spike-timing-dependent plasticity.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
spk_in	in	AXI4-Stream	32
spk_out	out	AXI4-Stream	32

Standards

No external standard applies.

More in neuromorphic

ID	Block	Maturity
of_acc_snn_router	Spike event router	planned