IP PortfolioCompute acceleratorshpc
of_acc_fft
Streaming FFT engine
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Pipelined mixed-radix FFT and IFFT with run-time size from 16 to 64k points, fixed or floating point, natural or bit-reversed order.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| x_in | in | AXI4-Stream | 64 | |
| y_out | out | AXI4-Stream | 64 |
Standards
- IEEE 754-2019
More in hpc
| ID | Block | Maturity |
|---|---|---|
| of_acc_blas | BLAS engine | planned |
| of_acc_spmv_graph | Sparse matrix and graph engine | planned |
| of_acc_stencil | Stencil computation engine | planned |
| of_acc_md_forces | Molecular dynamics force pipeline | planned |
| of_acc_monte_carlo | Monte Carlo engine | planned |
| of_acc_seq_align | Sequence alignment engine | planned |
| of_acc_matrix_decomp | Matrix decomposition engine | planned |
| of_acc_sort | Sorting engine | planned |
| of_acc_ising | Digital annealer | planned |
| of_acc_cgra | Coarse-grained reconfigurable array | planned |