IP PortfolioCompute acceleratorshpc
of_acc_cgra
Coarse-grained reconfigurable array
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Array of word-level processing elements with a configurable interconnect, mapped by a compiler for dataflow kernels.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
No external standard applies.
More in hpc
| ID | Block | Maturity |
|---|---|---|
| of_acc_fft | Streaming FFT engine | simulated |
| of_acc_blas | BLAS engine | planned |
| of_acc_spmv_graph | Sparse matrix and graph engine | planned |
| of_acc_stencil | Stencil computation engine | planned |
| of_acc_md_forces | Molecular dynamics force pipeline | planned |
| of_acc_monte_carlo | Monte Carlo engine | planned |
| of_acc_seq_align | Sequence alignment engine | planned |
| of_acc_matrix_decomp | Matrix decomposition engine | planned |
| of_acc_sort | Sorting engine | planned |
| of_acc_ising | Digital annealer | planned |