IP PortfolioVerification IPverification infrastructure
of_vip_ral_gen
Register model generator
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Generates UVM register models, cocotb register classes, C headers and documentation from SystemRDL or IP-XACT, with built-in reset, bit-bash and access-policy sequences.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- Accellera SystemRDL 2.0
- IEEE 1685-2022
- IEEE 1800.2-2020
More in verification infrastructure
| ID | Block | Maturity |
|---|---|---|
| of_vip_scoreboard | Transaction scoreboard | simulated |
| of_vip_coverage | Functional coverage collector | simulated |
| of_vip_mem_model | Sparse memory model | simulated |
| of_vip_clk_rst_gen | Clock and reset generator | simulated |
| of_vip_irq_mon | Interrupt monitor | planned |
| of_vip_gpio_agent | GPIO pin agent | planned |
| of_vip_stream_tg | Stream traffic generator and checker | simulated |
| of_vip_cdc_assert | CDC and reset assertion library | planned |
| of_vip_power_aware | Power-aware checker | planned |
| of_vip_formal_props | Bus protocol formal property sets | simulated |