IP PortfolioVerification IPmemory interface vip
of_vip_onfi_model
ONFI NAND flash model
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Behavioral NAND flash model with ONFI command set, page/block organization, program and erase timing, bad blocks and bit-error injection for ECC testing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| io | inout | parallel | 8 | |
| ctrl | in | parallel | 6 |
Standards
- ONFI 5.1
More in memory interface vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_ddr4_mon | DDR4 monitor and protocol checker | planned |
| of_vip_ddr4_bfm | DDR4 SDRAM memory model | planned |
| of_vip_ddr5_mon | DDR5 monitor and protocol checker | planned |
| of_vip_ddr5_bfm | DDR5 SDRAM and DIMM memory model | planned |
| of_vip_lpddr_mon | LPDDR4/LPDDR5 monitor and protocol checker | planned |
| of_vip_lpddr_bfm | LPDDR4/LPDDR5 memory model | planned |
| of_vip_hbm_mon | HBM monitor and protocol checker | planned |
| of_vip_hbm_bfm | HBM memory model | planned |