IP PortfolioVerification IPhigh-speed serial vip
of_vip_cxl_bfm
CXL bus functional model and agent
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
CXL host and Type 1/2/3 device agents with HDM decoder setup, CXL.mem read/write flows, CXL.cache snoops and back-invalidation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| flit_tx | out | AXI4-Stream | 256 | |
| flit_rx | in | AXI4-Stream | 256 |
Standards
- CXL 3.1
More in high-speed serial vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_usb2_mon | USB 2.0 monitor and protocol checker | planned |
| of_vip_usb2_bfm | USB 2.0 bus functional model and agent | planned |
| of_vip_usb3_mon | USB 3.2 monitor and protocol checker | planned |
| of_vip_usb3_bfm | USB 3.2 bus functional model and agent | planned |
| of_vip_usb4_mon | USB4 monitor and protocol checker | planned |
| of_vip_usb4_bfm | USB4 bus functional model and agent | planned |
| of_vip_pcie_mon | PCI Express monitor and protocol checker | planned |
| of_vip_pcie_bfm | PCI Express bus functional model and agent | planned |
| of_vip_cxl_mon | CXL monitor and protocol checker | planned |