IP PortfolioSoC interconnectdebug_and_test
of_wrap_1500
IEEE 1500 core test wrapper
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
IEEE 1500 wrapper with WIR, WBY and boundary register supporting BYPASS, EXTEST, INTEST and SAFE over the serial port.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- IEEE 1500
Notes
Serial port only; no parallel port or WS_CLAMP yet.
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